LTC3411

sn3411 3411fs

The LTC

3411 is a constant frequency, synchronous,

step- down DC/DC converter. Intended for medium power
applications, it operates from a 2.63V to 5.5V input voltage
range and has a user configurable operating frequency up
to 4MHz, allowing the use of tiny, low cost capacitors and
inductors 2mm or less in height. The output voltage is
adjustable from 0.8V to 5V. Internal sychronous 0.11

power switches with 1.6A peak current ratings provide
high efficiency. The LTC3411's current mode architecture
and external compensation allow the transient response
to be optimized over a wide range of loads and output
capacitors.

The LTC3411 can be configured for automatic power
saving Burst Mode operation to reduce gate charge losses
when the load current drops below the level required for
continuous operation. For reduced noise and RF interfer-
ence, the SYNC/MODE pin can be configured to skip
pulses or provide forced continuous operation.

To further maximize battery life, the P-channel MOSFET is
turned on continuously in dropout (100% duty cycle) with
a low quiescent current of 60

A. In shutdown, the device

draws <1

Notebook Computers

Digital Cameras

Cellular Phones

Handheld Instruments

Board Mounted Power Supplies

, LTC and LT are registered trademarks of Linear Technology Corporation.

Small 10-Lead MSOP or DFN Package

Uses Tiny Capacitors and Inductor

High Frequency Operation: Up to 4MHz

High Switch Current: 1.6A

Low R

DS(ON)

Internal Switches: 0.110

High Efficiency: Up to 95%

Stable with Ceramic Capacitors

Current Mode Operation for Excellent Line
and Load Transient Response

Short-Circuit Protected

Low Dropout Operation: 100% Duty Cycle

Low Shutdown Current: I

Low Quiescent Current: 60

Output Voltages from 0.8V to 5V

Selectable Burst Mode

Operation

Sychronizable to External Clock

1.25A, 4MHz, Synchronous

Step-Down DC/DC Converter

Efficiency vs Load Current

Figure 1. Step-Down 2.5V/1.25A Regulator

Burst Mode is a registered trademark of Linear Technology Corporation.

DESCRIPTIO

FEATURES

APPLICATIO S

TYPICAL APPLICATIO

SYNC/MODE

LTC3411

PGOOD

SHDN/R

PGND

SGND

2.2

OUT

2.5V/1.25A

2.63V TO 5.5V

887k

412k

1000pF

3411 F01

C2
22

13k

C1
22

324k

NOTE: IN DROPOUT, THE OUTPUT TRACKS
THE INPUT VOLTAGE
C1, C2: TAIYO YUDEN JMK325BJ226MM
L1: TOKO A914BYW-2R2M (D52LC SERIES)

LOAD CURRENT (mA)

EFFICIENCY (%)

100

1000

3411 TA01

= 3.3V

OUT

= 2.5V

= 1MHz

Burst Mode OPERATION

LTC3411

sn3411 3411fs

, SV

Voltages ..................................... 0.3V to 6V

, I

, SHDN/R

Voltages .......... 0.3V to (V

+ 0.3V)

SYNC/MODE Voltage .................... 0.3V to (V

+ 0.3V)

SW Voltage ................................... 0.3V to (V

+ 0.3V)

PGOOD Voltage ........................................... 0.3V to 6V
Operating Ambient Temperature Range
(Note 2) .................................................. 40

C to 85

ORDER PART

NUMBER

DD PART MARKING

JMAX

= 125

= 120

C/W,

= 10

C/W

Consult LTC Marketing for parts specified with wider operating temperature ranges.

LADT

LTC3411EDD

ABSOLUTE AXI U

RATI GS

PACKAGE/ORDER I FOR ATIO

(Note 1)

1
2
3
4
5

SHDN/R

SYNC/MODE

SGND

PGND

10
9
8
7
6

PGOOD
SV

TOP VIEW

MS PACKAGE

10-LEAD PLASTIC MSOP

Junction Temperature (Notes 5, 8) ....................... 125

Storage Temperature Range

DD Package ...................................... 65

C to 125

MS Package .................................... 65

C to 150

Lead Temperature (Soldering, 10 sec).................. 300

ORDER PART

NUMBER

MS PART MARKING

LTQT

LTC3411EMS

TOP VIEW

DD PACKAGE

10-LEAD (3mm

3mm) PLASTIC DFN

PGOOD

SHDN/R

SYNC/MODE

SGND

PGND

JMAX

= 125

= 43

C/W,

= 3

C/W

(EXPOSED PAD MUST BE SOLDERED TO PCB)

ELECTRICAL CHARACTERISTICS

The

denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T

= 25

C. V

= 3.3V, R

= 324k unless otherwise specified. (Note 2)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Operating Voltage Range

2.625

5.5

Feedback Pin Input Current

(Note 3)

0.1

Feedback Voltage

(Note 3)

0.784

0.8

0.816

LINEREG

Reference Voltage Line Regulation

= 2.7V to 5V

0.04

0.2

%/V

LOADREG

Output Voltage Load Regulation

= 0.36, (Note 3)

0.02

0.2

= 0.84, (Note 3)

0.02

0.2

m(EA)

Error Amplifier Transconductance

Pin Load =

A (Note 3)

800

Input DC Supply Current (Note 4)

Active Mode

= 0.75V, SYNC/MODE = 3.3V

240

350

Sleep Mode

SYNC/MODE

= 3.3V, V

= 1V

100

Shutdown

SHDN/RT

= 3.3V

0.1

SHDN/RT

Shutdown Threshold High

0.6 V

0.4

Active Oscillator Resistor

324k

OSC

Oscillator Frequency

= 324k

0.85

1.15

MHz

(Note 7)

MHz

SYNC

Synchronization Frequency

(Note 7)

0.4

MHz

LIM

Peak Switch Current Limit

= 1.3

1.6

DS(ON)

Top Switch On-Resistance (Note 6)

= 3.3V

0.11

0.15

Bottom Switch On-Resistance (Note 6)

= 3.3V

0.11

0.15

SW(LKG)

Switch Leakage Current

= 6V, V

ITH/RUN

= 0V, V

= 0V

0.01

UVLO

Undervoltage Lockout Threshold

Ramping Down

2.375

2.5

2.625

LTC3411

sn3411 3411fs

ELECTRICAL CHARACTERISTICS

The

denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T

= 25

C. V

= 3.3V, R

= 324k unless otherwise specified. (Note 2)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

PGOOD

Power Good Threshold

Ramping Up, SHDN/R

= 1V

6.8

Ramping Down, SHDN/R

= 1V

7.6

PGOOD

Power Good Pull-Down On-Resistance

118

200

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.

Note 2: The LTC3411E is guaranteed to meet specified performance from
0

C to 70

C. Specifications over the 40

C to 85

C operating ambient

termperature range are assured by design, characterization and correlation
with statistical process controls.

Note 3: The LTC3411 is tested in a feedback loop which servos V

to the

midpoint for the error amplifier (V

ITH

= 0.6V).

Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.

Note 5: T

is calculated from the ambient T

and power dissipation P

according to the following formula:

LTC3411EDD: T

= T

+ (P

· 43

C/W)

LTC3411EMS: T

= T

+ (P

· 120

C/W)

Note 6: Switch on-resistance is guaranteed by correlation to wafer level
measurements.

Note 7: 4MHz operation is guaranteed by design but not production tested
and is subject to duty cycle limitations (see Applications Information).

Note 8: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125

C when overtemperature protection is active.

Continuous operation above the specified maximum operating junction
temperature may impair device reliability.

PI FU CTIO S

SHDN/R

(Pin 1): Combination Shutdown and Timing

Resistor Pin. The oscillator frequency is programmed by
connecting a resistor from this pin to ground. Forcing this
pin to SV

causes the device to be shut down. In shut-

down all functions are disabled.

SYNC/MODE (Pin 2): Combination Mode Selection and
Oscillator Synchronization Pin. This pin controls the op-
eration of the device. When tied to SV

or SGND, Burst

Mode operation or pulse skipping mode is selected, re-
spectively. If this pin is held at half of SV

, the forced

continuous mode is selected. The oscillation frequency
can be syncronized to an external oscillator applied to this
pin. When synchronized to an external clock pulse skip
mode is selected.

SGND (Pin 3): The Signal Ground Pin. All small signal
components and compensation components should be
connected to this ground (see Board Layout Consider-
ations).

SW (Pin 4): The Switch Node Connection to the Inductor.
This pin swings from PV

to PGND.

PGND (Pin 5): Main Power Ground Pin. Connect to the
() terminal of C

OUT

, and () terminal of C

(Pin 6): Main Supply Pin. Must be closely decoupled

to PGND.

(Pin 7): The Signal Power Pin. All active circuitry is

powered from this pin. Must be closely decoupled to
SGND. SV

must be greater than or equal to PV

PGOOD (Pin 8): The Power Good Pin. This common drain
logic output is pulled to SGND when the output voltage is
not within

7.5% of regulation.

(Pin 9): Receives the feedback voltage from the

external resistive divider across the output. Nominal volt-
age for this pin is 0.8V.

(Pin 10): Error Amplifier Compensation Point. The

current comparator threshold increases with this control
voltage. Nominal voltage range for this pin is 0V to 1.5V.

LTC3411

sn3411 3411fs

NOMINAL (V)

ABSOLUTE MAX (V)

PIN

NAME

DESCRIPTION

MIN

TYP

MAX

MIN

MAX

SHDN/R

Shutdown/Timing Resistor

0.3

0.8

0.3

+ 0.3

SYNC/MODE

Mode Select/Sychronization Pin

0.3

+ 0.3

SGND

Signal Ground

Switch Node

0.3

+ 0.3

PGND

Main Power Ground

Main Power Supply

0.3

5.5

0.3

+ 0.3

Signal Power Supply

2.5

5.5

0.3

PGOOD

Power Good Pin

0.3

Output Feedback Pin

0.8

1.0

0.3

+ 0.3

Error Amplifier Compensation and Run Pin

1.5

0.3

+ 0.3

PI FU CTIO S

TYPICAL PERFOR A CE CHARACTERISTICS

Burst Mode Operation

Pulse Skipping Mode

Forced Continuous Mode

= 3.3V

s/DIV

3411 G01.eps

OUT

= 2.5V

LOAD

= 50mA

CIRCUIT OF FIGURE 7

= 3.3V

s/DIV

3411 G02.eps

OUT

= 2.5V

LOAD

= 50mA

CIRCUIT OF FIGURE 7

LOAD CURRENT (mA)

EFFICIENCY (%)

100

1000

10000

3411 G04

= 3.3V

OUT

= 2.5V

CIRCUIT OF FIGURE 7

Burst Mode

OPERATION

PULSE SKIP

FORCED CONTINUOUS

Efficiency vs Load Current

= 3.3V

s/DIV

3411 G03.eps

OUT

= 2.5V

LOAD

= 50mA

CIRCUIT OF FIGURE 7

OUT

10mV/

DIV

100mA/

DIV

OUT

10mV/

DIV

100mA/

DIV

OUT

10mV/

DIV

100mA/

DIV

2.5

3.5

4.5

5.5

(V)

EFFICIENCY (%)

100

3411 G05

OUT

= 400mA

OUT

= 1.25A

OUT

= 2.5V

CIRCUIT OF FIGURE 7

Efficiency vs V

Load Step

= 3.3V

s/DIV

3411 G06.eps

OUT

= 2.5V

LOAD

= 0.25mA TO 1.25A

CIRCUIT OF FIGURE 7

OUT

100mV/

DIV

0.5A/

DIV

LTC3411

sn3411 3411fs

100

1000

10000

LOAD CURRENT (mA)

OUT

ERROR (%)

0.4

0.3

0.2

0.1

0.2

0.3

0.4

0.5

3411 G07

Burst Mode
OPERATION

PULSE SKIP

FORCED

CONTINUOUS

= 3.3V

OUT

= 2.5V

(V)

OUT

ERROR (%)

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

3411 G08

OUT

= 1.8V

= 25

OUT

= 1.25A

OUT

= 400mA

(V)

FREQUENCY VARIATION (%)

3411 G09

OUT

= 1.8V

OUT

= 1.25A

= 25

Load Regulation

Line Regulation

Frequency vs V

TYPICAL PERFOR A CE CHARACTERISTICS

2.5

3.5

4.5

5.5

(V)

DS(ON)

)

120

115

110

105

100

3411 G12

MAIN SWITCH

SYNCHRONOUS SWITCH

= 25

Frequency Variation
vs Temperature

DS(ON)

vs V

100

125

TEMPERATURE (

REFERENCE VARIATION (%)

3411 G10

FREQUENCY (MHz)

EFFICIENCY (%)

100

3411 G11

= 3.3V

OUT

= 2.5V

OUT

= 500mA

= 25

Efficiency vs Frequency

LTC3411

sn3411 3411fs

OPERATIO

The LTC3411 uses a constant frequency, current mode
architecture. The operating frequency is determined by
the value of the R

resistor or can be synchronized to an

external oscillator. To suit a variety of applications, the
selectable Mode pin, allows the user to trade-off noise for
efficiency.

The output voltage is set by an external divider returned to
the V

pin. An error amplfier compares the divided output

voltage with a reference voltage of 0.8V and adjusts the
peak inductor current accordingly. Overvoltage and
undervoltage comparators will pull the PGOOD output low
if the output voltage is not within

7.5%.

Main Control Loop

During normal operation, the top power switch (P-channel
MOSFET) is turned on at the beginning of a clock cycle
when the V

voltage is below the the reference voltage.

The current into the inductor and the load increases until
the current limit is reached. The switch turns off and
energy stored in the inductor flows through the bottom
switch (N-channel MOSFET) into the load until the next
clock cycle.

The peak inductor current is controlled by the voltage on
the I

pin, which is the output of the error amplifier.This

amplifier compares the V

pin to the 0.8V reference.

When the load current increases, the V

voltage de-

creases slightly below the reference. This decrease causes
the error amplifier to increase the I

voltage until the

average inductor current matches the new load current.

The main control loop is shut down by pulling the SHDN/R

pin to SV

. A digital soft-start is enabled after shutdown,

which will slowly ramp the peak inductor current up over
1024 clock cycles or until the output reaches regulation,
whichever is first. Soft-start can be lengthened by ramping
the voltage on the I

pin (see Applications Information

section).

Low Current Operation

Three modes are available to control the operation of the
LTC3411 at low currents. All three modes automatically
switch from continuous operation to to the selected mode
when the load current is low.

To optimize efficiency, the Burst Mode

operation can be

selected. When the load is relatively light, the LTC3411
automatically switches into Burst Mode

operation in which

the PMOS switch operates intermittently based on load
demand. By running cycles periodically, the switching
losses which are dominated by the gate charge losses of
the power MOSFETs are minimized. The main control loop
is interrupted when the output voltage reaches the desired
regulated value. The hysteretic voltage comparator B trips
when I

is below 0.24V, shutting off the switch and

reducing the power. The output capacitor and the inductor
supply the power to the load until I

/RUN exceeds 0.31V,

turning on the switch and the main control loop which
starts another cycle.

For lower output voltage ripple at low currents, pulse
skipping mode can be used. In this mode, the LTC3411
continues to switch at a constant frequency down to very
low currents, where it will eventually begin skipping pulses.

Finally, in forced continuous mode, the inductor current is
constantly cycled which creates a fixed output voltage
ripple at all output current levels. This feature is desirable
in telecommunications since the noise is at a constant
frequency and is thus easy to filter out. Another advantage
of this mode is that the regulator is capable of both
sourcing current into a load and sinking some current
from the output.

Dropout Operation

When the input supply voltage decreases toward the
output voltage, the duty cycle increases to 100% which is
the dropout condition. In dropout, the PMOS switch is
turned on continuously with the output voltage being
equal to the input voltage minus the voltage drops across
the internal P-channel MOSFET and the inductor.

Low Supply Operation

The LTC3411 incorporates an undervoltage lockout circuit
which shuts down the part when the input voltage drops
below about 2.5V to prevent unstable operation.

LTC3411

sn3411 3411fs

APPLICATIO S I FOR ATIO

A general LTC3411 application circuit is shown in
Figure 5. External component selection is driven by the
load requirement, and begins with the selection of the
inductor L1. Once L1 is chosen, C

and C

OUT

can be

selected.

Operating Frequency

Selection of the operating frequency is a tradeoff between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge losses but requires larger
inductance values and/or capacitance to maintain low
output ripple voltage.

The operating frequency, f

, of the LTC3411 is determined

by an external resistor that is connected between the R

pin and ground. The value of the resistor sets the ramp
current that is used to charge and discharge an internal
timing capacitor within the oscillator and can be calculated
by using the following equation:

( )

9 78 10

1 08

or can be selected using Figure 2.

The maximum usable operating frequency is limited by the
minimum on-time and the duty cycle. This can be calcu-
lated as:

O(MAX)

6.67 · (V

OUT

/ V

IN(MAX)

) (MHz)

The minimum frequency is limited by leakage and noise
coupling due to the large resistance of R

Inductor Selection

Although the inductor does not influence the operating
frequency, the inductor value has a direct effect on ripple
current. The inductor ripple current

decreases with

higher inductance and increases with higher V

or V

OUT

· 1

Accepting larger values of

allows the use of low

inductances, but results in higher output voltage ripple,
greater core losses, and lower output current capability.

A reasonable starting point for setting ripple current is

= 0.3 · I

LIM

, where I

LIM

is the peak switch current limit.

The largest ripple current

occurs at the maximum

input voltage. To guarantee that the ripple current stays
below a specified maximum, the inductor value should be
chosen according to the following equation:

OUT

IN MAX

(

)

The inductor value will also have an effect on Burst Mode
operation. The transition from low current operation begins
when the peak inductor current falls below a level set by the
burst clamp. Lower inductor values result in higher ripple
current which causes this to occur at lower load currents.
This causes a dip in efficiency in the upper range of low
current operation. In Burst Mode operation, lower induc-
tance values will cause the burst frequency to increase.

)

FREQUENCY (MHz)

0.5

1.5

2.0

2.5

1000

4.5

= 25

3411 F02

1.0

500

1500

3.0

3.5

4.0

Figure 2. Frequency vs R

Inductor Core Selection

Different core materials and shapes will change the size/
current and price/current relationship of an inductor. Tor-
oid or shielded pot cores in ferrite or permalloy materials
are small and don't radiate much energy, but generally cost
more than powdered iron core inductors with similar
electrical characteristics. The choice of which style induc-
tor to use often depends more on the price vs size require-
ments and any radiated field/EMI requirements than on
what the LTC3411 requires to operate. Table 1 shows some

LTC3411

sn3411 3411fs

APPLICATIO S I FOR ATIO

typical surface mount inductors that work well in LTC3411
applications.

Table 1. Representative Surface Mount Inductors

MANU-

MAX DC

FACTURER PART NUMBER

VALUE CURRENT DCR HEIGHT

Toko

A914BYW-2R2M-D52LC 2.2

2.05A

49m

2mm

Toko

A915AY-2ROM-D53LC

3.3A

22m

3mm

Coilcraft

D01608C-222

2.2

2.3A

70m

3mm

Coilcraft

LP01704-222M

2.2

2.4A

120m

1mm

Sumida

CDRH4D282R2

2.2

2.04A

23m

3mm

Sumida

CDC5D232R2

2.2

2.16A

30m

2.5mm

Taiyo Yuden N06DB2R2M

2.2

3.2A

29m

3.2mm

Taiyo Yuden N05DB2R2M

2.2

2.9A

32m

2.8mm

Murata

LQN6C2R2M04

2.2

3.2A

24m

5mm

Catch Diode Selection

Although unnecessary in most applications, a small im-
provement in efficiency can be obtained in a few applica-
tions by including the optional diode D1 shown in Figure 5,
which conducts when the synchronous switch is off.
When using Burst Mode operation or pulse skip mode, the
synchronous switch is turned off at a low current and the
remaining current will be carried by the optional diode. It
is important to adequately specify the diode peak current
and average power dissipation so as not to exceed the
diode ratings. The main problem with Schottky diodes is
that their parasitic capacitance reduces the efficiency,
usually negating the possible benefits for LTC3411 cir-
cuits. Another problem that a Schottky diode can intro-
duce is higher leakage current at high temperatures, which
could reduce the low current efficiency.

Remember to keep lead lengths short and observe proper
grounding (see Board Layout Considerations) to avoid
ringing and increased dissipation when using a catch
diode.

Input Capacitor (C

) Selection

In continuous mode, the input current of the converter is
a square wave with a duty cycle of approximately V

OUT

. To prevent large voltage transients, a low equivalent

series resistance (ESR) input capacitor sized for the maxi-
mum RMS current must be used. The maximum RMS
capacitor current is given by:

RMS

MAX

OUT

(

)

where the maximum average output current I

MAX

equals

the peak current minus half the peak-to-peak ripple cur-
rent, I

MAX

= I

LIM

/2.

This formula has a maximum at V

= 2V

OUT

, where

RMS

= I

OUT

/2. This simple worst case is commonly used

to design because even significant deviations do not offer
much relief. Note that capacitor manufacturer's ripple
current ratings are often based on only 2000 hours life-
time. This makes it advisable to further derate the capaci-
tor, or choose a capacitor rated at a higher temperature
than required. Several capacitors may also be paralleled to
meet the size or height requirements of the design. An
additional 0.1

F to 1

F ceramic capacitor is also recom-

mended on V

for high frequency decoupling, when not

using an all ceramic capacitor solution.

Output Capacitor (C

OUT

) Selection

The selection of C

OUT

is driven by the required ESR to

minimize voltage ripple and load step transients. Typically,
once the ESR requirement is satisfied, the capacitance is
adequate for filtering. The output ripple (

OUT

) is deter-

mined by:

I ESR

f C

OUT

O OUT

where f = operating frequency, C

OUT

= output capacitance

and

= ripple current in the inductor. The output ripple

is highest at maximum input voltage since

increases

with input voltage. With

= 0.3 · I

LIM

the output ripple

will be less than 100mV at maximum V

and f

= 1MHz

with:

ESRC

OUT

< 150m

LTC3411

sn3411 3411fs

Once the ESR requirements for C

OUT

have been met, the

RMS current rating generally far exceeds the I

RIPPLE(P-P)

requirement, except for an all ceramic solution.

In surface mount applications, multiple capacitors may
have to be paralleled to meet the capacitance, ESR or RMS
current handling requirement of the application. Alumi-
num electrolytic, special polymer, ceramic and dry tantulum
capacitors are all available in surface mount packages.
The OS-CON semiconductor dielectric capacitor available
from Sanyo has the lowest ESR(size) product of any
aluminum electrolytic at a somewhat higher price. Special
polymer capacitors, such as Sanyo POSCAP, offer very
low ESR, but have a lower capacitance density than other
types. Tantalum capacitors have the highest capacitance
density, but it has a larger ESR and it is critical that the
capacitors are surge tested for use in switching power
supplies. An excellent choice is the AVX TPS series of
surface mount tantalums, avalable in case heights rang-
ing from 2mm to 4mm. Aluminum electrolytic capacitors
have a significantly larger ESR, and is often used in
extremely cost-sensitive applications provided that con-
sideration is given to ripple current ratings and long term
reliability. Ceramic capacitors have the lowest ESR and
cost but also have the lowest capacitance density, a high
voltage and temperature coefficient and exhibit audible
piezoelectric effects. In addition, the high Q of ceramic
capacitors along with trace inductance can lead to signifi-
cant ringing. Other capacitor types include the Panasonic
specialty polymer (SP) capacitors.

In most cases, 0.1

F to 1

F of ceramic capacitors should

also be placed close to the LTC3411 in parallel with the
main capacitors for high frequency decoupling.

Ceramic Input and Output Capacitors

Higher value, lower cost ceramic capacitors are now
becoming available in smaller case sizes. These are tempt-
ing for switching regulator use because of their very low
ESR. Unfortunately, the ESR is so low that it can cause
loop stability problems. Solid tantalum capacitor ESR
generates a loop "zero" at 5kHz to 50kHz that is instrumen-
tal in giving acceptable loop phase margin. Ceramic ca-

pacitors remain capacitive to beyond 300kHz and ususally
resonate with their ESL before ESR becomes effective.
Also, ceramic caps are prone to temperature effects which
requires the designer to check loop stability over the
operating temperature range. To minimize their large
temperature and voltage coefficients, only X5R or X7R
ceramic capacitors should be used. A good selection of
ceramic capacitors is available from Taiyo Yuden, TDK and
Murata.

Great care must be taken when using only ceramic input
and output capacitors. When a ceramic capacitor is used
at the input and the power is being supplied through long
wires, such as from a wall adapter, a load step at the output
can induce ringing at the V

pin. At best, this ringing can

couple to the output and be mistaken as loop instability. At
worst, the ringing at the input can be large enough to
damage the part.

Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge storage
requirement. During a load step, the output capacitor must
instantaneously supply the current to support the load
until the feedback loop raises the switch current enough to
support the load. The time required for the feedback loop
to respond is dependent on the compensation compo-
nents and the output capacitor size. Typically, 3 to 4 cycles
are required to respond to a load step, but only in the first
cycle does the output drop linearly. The output droop,
V

DROOP

, is usually about 2 to 3 times the linear drop of the

first cycle. Thus, a good place to start is with the output
capacitor size of approximately:

OUT

DROOP

2 5

More capacitance may be required depending on the duty
cycle and load step requirements.

In most applications, the input capacitor is merely re-
quired to supply high frequency bypassing, since the
impedance to the supply is very low. A 10

F ceramic

capacitor is usually enough for these conditions.

APPLICATIO S I FOR ATIO

LTC3411

sn3411 3411fs

Setting the Output Voltage

The LTC3411 develops a 0.8V reference voltage between
the feedback pin, V

, and the signal ground as shown in

Figure 5. The output voltage is set by a resistive divider
according to the following formula:

OUT

0 8

Keeping the current small (<5

A) in these resistors maxi-

mizes efficiency, but making them too small may allow
stray capacitance to cause noise problems and reduce the
phase margin of the error amp loop.

To improve the frequency response, a feed-forward ca-
pacitor C

may also be used. Great care should be taken to

route the V

line away from noise sources, such as the

inductor or the SW line.

Shutdown and Soft-Start

The SHDN/R

pin is a dual purpose pin that sets the

oscillator frequency and provides a means to shut down
the LTC3411. This pin can be interfaced with control logic
in several ways, as shown in Figure 3(a) and Figure 3(b).

The I

pin is primarily for loop compensation, but it can

also be used to increase the soft-start time. Soft start
reduces surge currents from V

by gradually increasing

the internal peak inductor current. Power supply sequenc-
ing can also be accomplished using this pin. The LTC3411
has an internal digital soft-start which steps up a clamp on
I

over 1024 clock cycles, as can be seen in Figure 4.

The soft-start time can be increased by ramping the
voltage on I

during start-up as shown in Figure 3(c). As

the voltage on I

ramps through its operating range the

internal peak current limit is also ramped at a proportional
linear rate.

Mode Selection and Frequency Synchronization

The SYNC/MODE pin is a multipurpose pin which provides
mode selection and frequency synchronization. Connect-
ing this pin to V

enables Burst Mode operation, which

provides the best low current efficiency at the cost of a
higher output voltage ripple. When this pin is connected to
ground, pulse skipping operation is selected which pro-
vides the lowest output voltage and current ripple at the
cost of low current efficiency. Applying a voltage within 1V
of the supplies, results in forced continuous mode, which
creates a fixed output ripple and is capable of sinking some
current (about 1/2

). Since the switching noise is con-

stant in this mode, it is also the easiest to filter out. In many
cases, the output voltage can be simply connected to the
SYNC/MODE pin, giving the forced continuous mode,
except at startup.

APPLICATIO S I FOR ATIO

Figure 3. SHDN/R

Pin Interfacing and External Soft-Start

3411 F03a

RUN

SHDN/R

3411 F03b

RUN

SHDN/R

3411 F03c

RUN OR V

(3c)

(3b)

(3a)

Figure 4. Digital Soft-Start

2V/DIV

OUT

2V/DIV

500mA/DIV

= 3.3V

200

s/DIV

3411 F04.eps

OUT

= 2.5V

= 1.4

LTC3411

sn3411 3411fs

The LTC3411 can also be synchronized to an external
clock signal by the SYNC/MODE pin. The internal oscillator
frequency should be set to 20% lower than the external
clock frequency to ensure adequate slope compensation,
since slope compensation is derived from the internal
oscillator. During synchronization, the mode is set to
pulse skipping and the top switch turn on is synchronized
to the rising edge of the external clock.

Checking Transient Response

The OPTI-LOOP compensation allows the transient re-
sponse to be optimized for a wide range of loads and
output capacitors. The availability of the I

pin not only

allows optimization of the control loop behavior but also
provides a DC coupled and AC filtered closed loop re-
sponse test point. The DC step, rise time and settling at this
test point truly reflects the closed loop response. Assum-
ing a predominantly second order system, phase margin
and/or damping factor can be estimated using the percent-
age of overshoot seen at this pin. The bandwidth can also
be estimated by examining the rise time at the pin.

The I

external components shown in the Figure 1 circuit

will provide an adequate starting point for most applica-
tions. The series R-C filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be selected

because the various types and values determine the loop
feedback factor gain and phase. An output current pulse of
20% to 100% of full load current having a rise time of 1

to 10

s will produce output voltage and I

pin waveforms

that will give a sense of the overall loop stability without
breaking the feedback loop.

Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, V

OUT

immediately shifts by an amount equal to

LOAD

· ESR,

where ESR is the effective series resistance of C

OUT

LOAD

also begins to charge or discharge C

OUT

generat-

ing a feedback error signal used by the regulator to return
V

OUT

to its steady-state value. During this recovery time,

OUT

can be monitored for overshoot or ringing that would

indicate a stability problem.

The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard second
order overshoot/DC ratio cannot be used to determine
phase margin. The gain of the loop increases with R and
the bandwidth of the loop increases with decreasing C. If
R is increased by the same factor that C is decreased, the
zero frequency will be kept the same, thereby keeping the
phase the same in the most critical frequency range of the
feedback loop. In addition, a feedforward capacitor C

can

be added to improve the high frequency response, as
shown in Figure 5. Capacitor C

provides phase lead by

creating a high frequency zero with R2 which improves the
phase margin.

APPLICATIO S I FOR ATIO

LTC3411

PGOOD

SYNC/MODE

SHDN/R

D1
OPTIONAL

2.5V

TO 5.5V

SGND PGND

3411 F05

ITH

OUT

PGND

SGND

PGND

SGND

SGND SGND

GND

PGND

OUT

SGND

Figure 5. LTC3411 General Schematic

LTC3411

sn3411 3411fs

The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance. For a detailed
explanation of optimizing the compensation components,
including a review of control loop theory, refer to Linear
Technology Application Note 76.

Although a buck regulator is capable of providing the full
output current in dropout, it should be noted that as the
input voltage V

drops toward V

OUT

, the load step capa-

bility does decrease due to the decreasing voltage across
the inductor. Applications that require large load step
capability near dropout should use a different topology
such as SEPIC, Zeta or single inductor, positive buck/
boost.

In some applications, a more severe transient can be
caused by switching in loads with large (>1uF) input
capacitors. The discharged input capacitors are effectively
put in parallel with C

OUT

, causing a rapid drop in V

OUT

. No

regulator can deliver enough current to prevent this prob-
lem, if the switch connecting the load has low resistance
and is driven quickly. The solution is to limit the turn-on
speed of the load switch driver. A hot swap controller is
designed specifically for this purpose and usually incorpo-
rates current limiting, short-circuit protection, and soft-
starting.

Efficiency Considerations

The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:

%Efficiency = 100% (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percentage
of input power.

Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3411 circuits: 1) LTC3411 V

current,

2) switching losses, 3) I

R losses, 4) other losses.

1) The V

current is the DC supply current given in the

electrical characteristics which excludes MOSFET driver
and control currents. V

current results in a small (<0.1%)

loss that increases with V

, even at no load.

2) The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current results
from switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high to
low again, a packet of charge dQ moves from V

ground. The resulting dQ/dt is a current out of V

that is

typically much larger than the DC bias current. In continu-
ous mode, I

GATECHG

= f

(QT + QB), where QT and QB are

the gate charges of the internal top and bottom MOSFET
switches. The gate charge losses are proportional to V

and thus their effects will be more pronounced at higher
supply voltages.

3) I

R Losses are calculated from the DC resistances of the

internal switches, R

, and external inductor, RL. In

continuous mode, the average output current flowing
through inductor L but is "chopped" between the internal
top and bottom switches. Thus, the series resistance
looking into the SW pin is a function of both top and
bottom MOSFET R

DS(ON)

and the duty cycle (DC) as

follows:

= (R

DS(ON)

TOP)(DC) + (R

DS(ON)

BOT)(1 DC)

The R

DS(ON)

for both the top and bottom MOSFETs can be

obtained from the Typical Performance Characteristics
curves. Thus, to obtain I

R losses:

R losses = I

OUT

2(R

+ RL)

4) Other "hidden" losses such as copper trace and internal
battery resistances can account for additional efficiency
degradations in portable systems. It is very important to
include these "system" level losses in the design of a
system. The internal battery and fuse resistance losses
can be minimized by making sure that C

has adequate

charge storage and very low ESR at the switching fre-
quency. Other losses including diode conduction losses
during dead-time and inductor core losses generally ac-
count for less than 2% total additional loss.

APPLICATIO S I FOR ATIO

LTC3411

sn3411 3411fs

Thermal Considerations

In a majority of applications, the LTC3411 does not
dissipate much heat due to its high efficiency. However, in
applications where the LTC3411 is running at high ambi-
ent temperature with low supply voltage and high duty
cycles, such as in dropout, the heat dissipated may exceed
the maximum junction temperature of the part. If the
junction temperature reaches approximately 150

C, both

power switches will be turned off and the SW node will
become high impedance.

To avoid the LTC3411 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:

RISE

= P

where P

is the power dissipated by the regulator and

is the thermal resistance from the junction of the die to the
ambient temperature.

The junction temperature, T

, is given by:

= T

RISE

+ T

AMBIENT

As an example, consider the case when the LTC3411 is in
dropout at an input voltage of 3.3V with a load current of
1A. From the Typical Performance Characteristics graph
of Switch Resistance, the R

DS(ON)

resistance of the

P-channel switch is 0.11

. Therefore, power dissipated

by the part is:

= I

· R

DS(ON)

= 110mW

The MS10 package junction-to-ambient thermal resis-
tance,

, will be in the range of 100

C/W to 120

C/W.

Therefore, the junction temperature of the regulator oper-
ating in a 70

C ambient temperature is approximately:

= 0.11 · 120 + 70 = 83.2

Remembering that the above junction temperature is
obtained from an R

DS(ON)

at 25

C, we might recalculate

the junction temperature based on a higher R

DS(ON)

since

it increases with temperature. However, we can safely

APPLICATIO S I FOR ATIO

assume that the actual junction temperature will not
exceed the absolute maximum junction temperature of
125

Design Example

As a design example, consider using the LTC3411 in a
portable application with a Li-Ion battery. The battery
provides a V

= 2.5V to 4.2V. The load requires a maxi-

mum of 1A in active mode and 10mA in standby mode. The
output voltage is V

OUT

= 2.5V. Since the load still needs

power in standby, Burst Mode operation is selected for
good low load efficiency.

First, calculate the timing resistor:

MHz

(

)

9 78 10

323 8

1 08

Use a standard value of 324k. Next, calculate the inductor
value for about 30% ripple current at maximum V

MHz

V
V

= µ

2 5

510

2 5
4 2

.
.

Choosing the closest inductor from a vendor of 2.2

results in a maximum ripple current of:

MHz

V
V

2 5

2 2

2 5
4 2

460

· .

.
.

For cost reasons, a ceramic capacitor will be used. C

OUT

selection is then based on load step droop instead of ESR
requirements. For a 5% output droop:

MHz

OUT

= µ

2 5

· ( %· .

)

The closest standard value is 22

F. Since the output

impedance of a Li-Ion battery is very low, C

is typically

F. In noisy environments, decoupling SV

from PV

with an R6/C8 filter of 1

/0.1

F may help, but is typically

not needed.

The output voltage can now be programmed by choosing
the values of R1 and R2. To maintain high efficiency, the

LTC3411

sn3411 3411fs

current in these resistors should be kept small. Choosing
2

A with the 0.8V feedback voltage makes R1~400k. A

close standard 1% resistor is 412k and R2 is then 887k.

The compensation should be optimized for these compo-
nents by examining the load step response but a good
place to start for the LTC3411 is with a 13k

and 1000pF

filter. The output capacitor may need to be increased
depending on the actual undershoot during a load step.

The PGOOD pin is a common drain output and requires a
pull-up resistor. A 100k resistor is used for adequate
speed.

Figure 1 shows the complete schematic for this design
example.

Board Layout Considerations

When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3411. These items are also illustrated graphically in
the layout diagram of Figure 6. Check the following in your
layout:

1. Does the capacitor C

connect to the power V

(Pin 6)

and power GND (Pin 5) as close as possible? This

capacitor provides the AC current to the internal power
MOSFETs and their drivers.

2. Are the C

OUT

and L1 closely connected? The () plate of

OUT

returns current to PGND and the () plate of C

3. The resistor divider, R1 and R2, must be connected
between the (+) plate of C

OUT

and a ground line terminated

near SGND (Pin 3). The feedback signal V

should be

routed away from noisy components and traces, such as
the SW line (Pin 4), and its trace should be minimized.

4. Keep sensitive components away from the SW pin. The
input capacitor C

, the compensation capacitor C

and

ITH

and all the resistors R1, R2, R

, and R

should be

routed away from the SW trace and the inductor L1.

5. A ground plane is preferred, but if not available, keep the
signal and power grounds segregated with small signal
components returning to the SGND pin at one point which
is then connected to the PGND pin.

6. Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise of
power components. These copper areas should be con-
nected to one of the input supplies: PV

, PGND, SV

SGND.

APPLICATIO S I FOR ATIO

LTC3411

PGND

SGND

PGOOD

SYNC/MODE

SHDN/R

OUT

3411 F06

BOLD LINES INDICATE HIGH CURRENT PATHS

OUT

Figure 6. LTC3411 Layout Diagram (See Board Layout Checklist)

LTC3411

sn3411 3411fs

Figure 7. General Purpose Buck Regulator Using Ceramic Capacitors

LTC3411

PGOOD

SYNC/MODE

SHDN/R

SGND

2.2

2.63V TO

5.5V

OUT

1.8V/2.5V/3.3V
AT 1.25A

R5
100k

R4
324k

R1A
280k

13k

RS1
1M

RS2

3411 F07a

C3
1000pF

C4 22pF

R2 887K

C2
22

SGND

R1B
412k

R1C
698k

PGND

SGND

NOTE: IN DROPOUT, THE OUTPUT TRACKS THE INPUT VOLTAGE
C1, C2: TAIYO YUDEN JMK325BJ226MM
L1: TOKO A914BYW-2R2M (D52LC SERIES)

GND

3.3V

2.5V

1.8V

LOAD CURRENT (mA)

EFFICIENCY (%)

100

1000

10000

3411 F07b

PULSE SKIP
(PS)

FORCED
CONTINUOUS (FC)

= 3.3V

OUT

= 2.5V

= 1MHz

Burst Mode

OPERATION (BM)

TYPICAL APPLICATIO S

Efficiency vs Load Current

LTC3411

sn3411 3411fs

All Ceramic 2-Cell to 3.3V and 1.8V Converters

TYPICAL APPLICATIO S

LTC3402

SHDN

MODE/SYNC

PGOOD

OUT

GND

1000pF

10pF

2
CELLS

47k

49.9k

604k

OUT

3.3V
120mA/1A

4.7

C2
44

C1: TAIYO YUDEN JMK212BJ106MG
C2: TAIYO YUDEN JMK325BJ226MM
C5, C6: TAIYO YUDEN JMK325BJ226MM

= 2V TO 3V

0 = FIXED FREQ

1 = Burst Mode OPERATION

SYNC/MODE

LTC3411

PGOOD

SHDN/R

PGND

SGND

2.2

OUT

1.8V/1.2A

887k

412k

1000pF

3411 TA06

C6
22

13k

C5
22

324k

D1: ON SEMICONDUCTOR MBRM120LT3
L1: TOKO A916CY-4R7M
L2: TOKO A914BYW-2R2M (D52LC SERIES)

LOAD CURRENT (mA)

EFFICIENCY (%)

100

1000

10000

3211 TA07

3.3V

1.8V

= 2.4V

Burst Mode OPERATION

Efficiency vs Load Current

LTC3411

sn3411 3411fs

PACKAGE DESCRIPTIO

MS10 Package

10-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1661)

MSOP (MS) 0402

0.53

0.01

(.021

.006)

SEATING

PLANE

0.18

(.007)

1.10

(.043)

MAX

0.17 0.27

(.007 .011)

0.13

0.05

(.005

.002)

0.86

(.034)

REF

0.50

(.0197)

TYP

1 2 3 4 5

4.88

0.10

(.192

.004)

0.497

0.076

(.0196

.003)

REF

7 6

3.00

0.102

(.118

.004)

(NOTE 3)

3.00

0.102

(.118

.004)

NOTE 4

NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

0.254

(.010)

TYP

DETAIL "A"

GAUGE PLANE

5.23

(.206)

MIN

3.2 3.45

(.126 .136)

0.889

0.127

(.035

.005)

RECOMMENDED SOLDER PAD LAYOUT

0.305

0.038

(.0120

.0015)

TYP

0.50

(.0197)

BSC

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

DD Package

10-Lead Plastic DFN (3mm

3mm)

(Reference LTC DWG # 05-08-1699)

3.00

0.10

(4 SIDES)

NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).

CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT

2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

0.38

0.10

BOTTOM VIEW--EXPOSED PAD

1.65

0.10

(2 SIDES)

0.75

0.05

R = 0.115

TYP

2.38

0.10

(2 SIDES)

PIN 1

TOP MARK

(SEE NOTE 5)

0.200 REF

0.00 0.05

(DD10) DFN 0403

0.25

0.05

2.38

0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

1.65

0.05

(2 SIDES)

2.15

0.05

0.50
BSC

0.675

0.05

3.50

0.05

PACKAGE
OUTLINE

0.25

0.05

0.50 BSC

LTC3411

sn3411 3411fs

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900

FAX: (408) 434-0507

www.linear.com

LINEAR TECHNOLOGY CORPORATION 2002

LT/TP 0503 2K · PRINTED IN USA

LTC3411

PGOOD

SYNC/MODE

SHDN/R

OUT

1.8V
AT 1.25A

2.63V

TO 4.2V

SGND PGND

R5
100k

C4 22pF

R4
154k

15k

R1
698k

887k

3411 TA04

470pF

47pF

C5
1

C1
33

C6
1

C1, C2: AVX TPSB336K006R0600
C4, C5: TAIYO YUDEN LMK212BJ105MG
L1: COILCRAFT DO1606T-102

C2
33

2mm Height, 2MHz, Li-Ion to 1.8V Converter

TYPICAL APPLICATIO

LOAD CURRENT (mA)

EFFICIENCY (%)

100

1000

10000

3411 TA05

OUT

= 1.8V

= 2MHz

2.5V

3.6V

4.2V

Efficiency vs Load Current

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ThinSOT is a trademark of Linear Technology Corporation.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LTC3411

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LTC3411